Semiconductor device and method for manufacturing the same

ABSTRACT

A semiconductor device includes a first insulating layer (interlayer insulating layer), a resistive element that is disposed over the first insulating layer (interlayer insulating layer) and at least a surface layer of which is a TaSiN layer, and an interlayer insulating layer disposed over the first insulating layer (interlayer insulating layer) and the resistive element. Multiple via plugs having ends coupled to the TaSiN layer are disposed in the interlayer insulating layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2011-243266 filed onNov. 7, 2011 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device and a method formanufacturing the same.

The resistance of a resistive element is preferably stable with respectto variations in the temperature of the environment. For this reason,resistive elements are required to have a smaller temperaturecoefficient of resistance. Various resistive elements, resistors, or thelike, including those described below, have been proposed.

Japanese Unexamined Patent Publication No. 2001-332402 discloses aresistive material. The resistive material essentially consists of fourelements-Al, B, Cr, and Si. The resistive element has a resistivity of 4mΩ·cm or more and an absolute temperature coefficient of resistance of300 ppm/° C. or less. Thus, the Publication states that it is possibleto provide a resistive element having a small absolute temperaturecoefficient of resistance and a large resistivity.

Japanese Unexamined Patent Publication No. 2007-073651 discloses athin-film resistor which is formed over a substrate having electricalinsulation properties and which contains a Cr-Al—Si ternary alloy. Byadjusting the composition ratio of the elements, the resistivity of thethin-film resistor becomes 500 μΩ·cm or more; the absolute temperaturecoefficient of resistance becomes 50 ppm/° C. or less; and the rate ofchange of the resistance after maintained at 155° C. for 1000 hoursbecomes 0.05% or less. Thus, the Publication states that it is possibleto provide a highly heat-resistant thin-film resistor which has a highresistivity and a low temperature coefficient of resistance and whichexhibits a low resistance change rate when heated during operation.

Japanese Unexamined Patent Publication No. 2008-010604 discloses athin-film resistive material that contains 20 to 60 mass % of Ta, 2 to10 mass % of Al, 0.5 to 15 mass % of Mo, and the balance containing Crand Ni where a mass ratio Cr/Ni is 0.75 to 1.1. Thus, the Publicationstates that a thin-film resistor using this thin-film resistive materialhas a significantly improved volume resistance and salt waterresistance, compared to a conventional thin-film resistor using aresistive thin film containing a Ni—Cr—Al—Si alloy.

Japanese Unexamined Patent Publication No. Hei6-275409 discloses thefollowing method for manufacturing a thin-film resistive element. A TaNlayer is formed by sputtering Ta in an atmosphere of a mixed gas of anoble gas element selected from the group consisting of Ne, Ar, Kr, andXe, and nitrogen. A noble gas element is sputtered onto the TaN layerusing a RF electrode apparatus. Thus, the Publication states that atemperature coefficient of resistance close to 0 ppm/° C. can beobtained stably without requiring vacuum annealing.

Japanese Unexamined Patent Publication No. 2004-342705 discloses thefollowing TaN thin-film resistor. An electrode film is formed over thetop surface of a TaN thin film formed over an insulating substrate withan intermediate film therebetween. Referring to the combined temperaturecoefficient of resistance of the intermediate film and the electrodefilm as a first temperature coefficient of resistance and to thetemperature coefficient of resistance of the thin-film resistor as asecond temperature coefficient of resistance, the sum of the first andsecond temperature coefficients of resistance is set to −10 ppm/° C. to0 ppm/° C. Thus, the Publication states that the temperature coefficientof resistance can be kept small across the entire operating temperatureregion in consideration of the contact resistance of the electrode film.

Japanese Unexamined Patent Publication No. 2009-021509 discloses asemiconductor device. The semiconductor device includes a resistiveelement containing nitrogen and tantalum as main constituent elementsdisposed over the main surface of a substrate. The top region of theresistive element, which is located opposite to the substrate, has anitrogen concentration of 30 at % or more. Thus, the Publication statesthat it is possible to provide a semiconductor device including aresistive element having a low parasitic capacitance and a resistancewhich varies to a lesser extent when subjected to heat treatment.

Japanese Unexamined Patent Publication No. 2002-043102 discloses athin-film resistor for inkjet printer. This thin-film resistor containsTaSiN having a high Si concentration. The TaSiN thin film has a Siconcentration (Si/(Si+Ta)) between 40% and 80% and a N concentrationbetween 2.5% and 50%. Thus, the Publication states that it is possibleto provide a thin-film resistor which has a high resistivity and a smalltemperature coefficient of resistance and which can be uniformly heatedas a heater material.

Japanese Unexamined Patent Publication No. Sho62-224002 discloses thefollowing method for manufacturing a thin-film chip resistor. First, aresistive film containing NiCr, TaN, or the like is deposited over anentire surface of a substrate by vapor deposition, sputtering, or thelike. Subsequently, a metal film to serve as an electrode is deposited.Subsequently, the resistive film is patterned. Further, a SiN film toserve as a protective film is formed over the resistive film by chemicalvapor deposition (CVD). Thus, the Publication states that it is possibleto provide a thin-film chip resistor which is significantly stable withrespect to the resistance and the rate of change thereof.

SUMMARY

Lithium-ion batteries have been widely used in recent years,particularly in mobile phones or the like. When mounting in electricvehicles, a multi-cell lithium ion battery is mounted thereon. Efficientuse of a multi-cell lithium ion battery requires monitoring of theremaining charge of each cell with high accuracy.

An external sense resistor is used in order to detect the remainingcharge with high accuracy. In particular, a wide range of operatingtemperatures must be assured in car-mounted applications. Accordingly,it is desired to minimize the temperature coefficient of resistance ofthe sense resistor itself.

In recent years, it is desired to form a resistive element as describedabove in the multilayer wiring of a semiconductor device as part of anintegrated circuit. For this reason, it is desired to minimize thetemperature coefficient of resistance as described in theabove-mentioned related-art examples, as well as to minimize the area ofthe element. Accordingly, a resistive element having a low temperaturecoefficient of resistance and a high resistivity is desired.

A first aspect of the present invention provides a semiconductor device.The semiconductor device includes: a first insulating layer; a resistiveelement that is disposed over the first insulating layer and at least asurface of which is a TaSiN layer; and an interlayer insulating layerdisposed over the first insulating layer and the resistive element.Multiple via plugs having ends coupled to the TaSiN layer are disposedin the interlayer insulating layer.

A second aspect of the present invention provides a method formanufacturing a semiconductor device. The method for manufacturing asemiconductor device includes: a step of forming a TaN layer over afirst insulating layer; a silane application step of modifying at leasta surface layer of the TaN layer to a TaSiN layer by applying aSi-containing gas; a step of forming an interlayer insulating layer overthe first insulating layer and the resistive element; and a step offorming multiple via plugs having ends coupled to the TaSiN layer in theinterlayer insulating layer.

According to the aspects of the present invention, the resistive elementat least the surface layer of which is the TaSiN layer is disposed overthe first insulating layer. The via plugs having ends coupled to theTaSiN layer are formed in the interlayer insulating layer disposed overthe first insulating layer and the resistive element. Thus, asemiconductor device can be provided that has a resistive element with ahigh resistivity and a small temperature coefficient of resistance inmultilayer wiring.

According to the aspects of the present invention, semiconductor devicecan be provided that has a resistive element with a high resistivity anda small temperature coefficient of resistance in multilayer wiring.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are sectional views showing the configuration of asemiconductor device according to a first embodiment;

FIG. 2 is a plan view showing the configuration of the semiconductordevice according to the first embodiment;

FIG. 3 is a circuit diagram showing the configuration of thesemiconductor device according to the first embodiment;

FIGS. 4A and 4B are sectional view showing a method for manufacturingthe semiconductor device according to the first embodiment;

FIGS. 5A and 5B are sectional views showing the method for manufacturingthe semiconductor device according to the first embodiment;

FIGS. 6A and 6B are sectional views showing the method for manufacturingthe semiconductor device according to the first embodiment;

FIGS. 7A and 7B are sectional views showing the method for manufacturingthe semiconductor device according to the first embodiment;

FIGS. 8A and 8B are diagrams showing the configuration of a resistiveelement according to a second embodiment;

FIGS. 9A and 9B are diagrams showing the configuration of a resistiveelement according to a third embodiment;

FIGS. 10A and 10B are diagrams showing the configuration of asemiconductor device according to a fourth embodiment; and

FIG. 11 is a sectional view showing the configuration of a semiconductordevice according to a fifth embodiment.

DETAILED DESCRIPTION

Now, embodiments of the present invention will be described withreference to the accompanying drawings. Like elements are given likereference signs throughout the drawings and therefore descriptionsthereof will be omitted as appropriate.

First Embodiment

Referring to FIGS. 1 and 2, a semiconductor device 10 according to afirst embodiment will be described. The semiconductor device 10 isconfigured as follows. That is, the semiconductor device 10 includes afirst insulating layer (interlayer insulating layer 340), a resistiveelement 400 which is disposed over the first insulating layer(interlayer insulating layer 340) and at least a surface layer of whichis a TaSiN layer 440, an interlayer insulating layer 360 disposed overthe first insulating layer (interlayer insulating layer 340) and theresistive element 400, and multiple via plugs 500 that are disposed inthe interlayer insulating layer 360 and that have ends coupled to theTaSiN layer 440. Details will be described below.

FIGS. 1A and 2B are sectional views showing the configuration of thesemiconductor device 10 according to the first embodiment, in which FIG.1B is a sectional view taken along line A-A′ of FIG. 1A.

As shown in FIG. 1A, a semiconductor substrate 100 includes elementisolation regions 120. The semiconductor substrate 100 is, for example,a silicon substrate. The element isolation regions 120 contain SiO₂ andare formed by local oxidation of silicon (LOCOS).

The semiconductor substrate 100 also has field effect transistors (FETs)in the region where the element isolation regions 120 are not formed.This region includes diffusion regions 140 serving as source regions ordrain regions and extension regions 160. Alternatively, this region mayinclude bipolar transistors.

A gate insulating layer 220 is disposed over channel regions (having noreference sign) interposed by the diffusion regions 140. Gate electrodes240 are disposed over the gate insulating layer 220. A sidewallinsulating layer 260 is disposed around both sides of the gateinsulating layer 220 and those of the gate electrodes 240.

A liner insulating layer 320 is disposed over these FETs. The linerinsulating layer 320 contains, for example, SiN.

A first insulating layer, an interlayer insulating layer 340, isdisposed over the liner insulating layer 320. The “first insulatinglayer” refers to an insulating layer disposed below the resistiveelement 400 to be discussed later. In the first embodiment, the firstinsulating layer is, for example, the interlayer insulating layer 340.The interlayer insulating layer 340 contains, for example, SiO₂, SiN,SiON, SiOC, SiOCH, SiCOH, or SiOF.

The first insulating layer may include multiple layers. If the firstinsulating layer, the interlayer insulating layer 340, includes a porousfilm such as a low-k film, a dense insulating layer (not shown) such asa SiCN layer may be disposed over the low-k film.

The resistive element 400 at least a surface layer of which is the TaSiNlayer 440 is disposed over the first insulating layer, the interlayerinsulating layer 340.

The “resistive element 400” refers to a resistive element including atleast the TaSiN layer 440. Broadly, a resistive element including a TaNlayer 420 to be discussed later or having the via plugs 500 serving asterminals may be referred to as the resistive element 400.

The TaSiN layer 440 is a modified layer formed by applying aSi-containing gas to the TaN layer 420. In other words, the TaSiN layer440 is a layer formed by doping the surface layer of the TaN layer 420with Si. In this embodiment, the ternary TaSiN layer 440 can easily beformed by forming the TaN layer 420 and then applying a Si-containinggas thereto. The silane application step of applying a Si-containing gaswill be described in detail later.

The resistive element 400 also includes the TaN layer 420 disposed overthe interlayer insulating layer 340. The TaSiN layer 440 is disposedover a surface layer of the TaN layer 420. As seen, where the resistiveelement 400 also includes the TaN layer 420, it is designed as aparallel circuit of the TaSiN layer 440 and the TaN layer 420.

The TaN layer 420 is 10 nm or more and 100 nm or less thick, preferably10 nm or more and 50 nm or less thick. The TaN layer 420 can be formedby reactive sputtering, as long as the thickness thereof falls withinthe above-mentioned range. For example, the TaN layer 420 is 20 nmthick.

The TaSiN layer 440 is 1 nm or more and 50 nm or less thick, preferably1 nm or more and 15 nm or less thick. The TaSiN layer 440 can be easilyformed in a silane application step to be discussed later, as long asthe thickness thereof falls within the above-mentioned range. Forexample, the TaSiN layer 440 is 5 nm thick.

As will be discussed later, in the manufacturing process, the TaN layer420 formation step is followed by the Si-containing gas application step(silane application step). Thus, the surface layer of the TaN layer 420is changed to silicide, forming the TaSiN layer 440. The inventors havefound that the temperature coefficient of resistance (TCR) and theresistivity of the TaSiN layer 440 can be controlled by adjusting thecomposition ratio Si/(Ta+Si) in the silane application step.

The absolute TCR of the resistive element 400 is 0 ppm/° C. or more and50 ppm/° C. or less, preferably 0 ppm/° C. or more and 25 ppm/° C. orless. A resistive element 400 whose resistance varies to a lesser extentin a wide operating temperature range can be obtained, as long as theTCR thereof falls within the above-mentioned range.

The sheet resistance of the TaSiN layer 440 is, for example, 10² Ω/sq ormore and 10⁷ Ω/sq or less. Such a high sheet resistance allows the areaof the resistive element to be reduced. Such a resistive element havinga reduced area can be disposed in the multilayer wiring of asemiconductor chip or the like.

The resistivity of the TaN layer 420 is adjusted according to thedesired resistivity of the TaSiN layer 440. The resistivity of the TaNlayer 420 can be adjusted by changing the composition ratio Ta/N. Forexample, the composition ratio Ta/N is 0.5 or more and 10 or less. Theresistivity of the TaN layer 420 serving as the source of the TaSiNlayer 440 can become 10² μΩ·cm or more and 10⁶ μΩ·cm or less, as long asthe composition ratio Ta/N falls within the above-mentioned range.

The composition ratio Si/(Ta+Si) of the TaSiN layer 440 is 0.5 or moreand 0.7 or less. A TaSiN layer 440 having the desired resistivity andTCR can be obtained as long as the composition ratio Si/(Ta+Si) fallswithin the above-mentioned range.

The TaN layer 420 formation step and the TaSiN layer 440 formation stepwill be described in detail later.

A SiN layer 460 is disposed over the resistive element 400.Specifically, the SiN layer 460 is disposed over the TaSiN layer 440. Aswill be discussed later, in the silane application step, the SiN layer460 as well as the TaSiN layer 440 are formed over the TaN layer 420. Asseen, in the silane application step, forming the SiN layer 460 over theTaN layer 420 allows the TaSiN layer 440 to be formed over the surfacelayer of the TaN layer 420. As a result, the resistive element 400having the above-mentioned configuration is obtained.

The SiN layer 460 serves also as an etching stopper film in the step offorming the via plugs 500. Accordingly, the SiN layer 460 is preferablyformed so as to have the same thickness as the liner insulating layer320. Thus, the formation of the via plugs 500 can be controlled underthe same etching condition in the step of forming the via plugs 500.

The SiN layer 460 need not necessarily be disposed over the TaSiN layer440. That is, the SiN layer 460 may be eliminated in the manufacturingprocess. However, the SiN layer 460 is preferably formed only overcontact portions 402 of the resistive element 400 to which the via plugs500 are coupled.

The TaSiN layer 440 is amorphous. The use of the TaSiN layer 440 that isamorphous, that is, isotropic controls variations in the characteristicsof the resistive element caused by thermal stress generated in theprocess of manufacturing the semiconductor device 10.

The interlayer insulating layer 360 is disposed over the interlayerinsulating layer 340 and the resistive element 400. The multiple viaplugs 500 are formed in the interlayer insulating layer 360. Some of thevia plugs 500 are in contact with the diffusion regions 140 of FETs atends thereof.

A via plug 500 is formed directly on the resistive element 400 in such amanner that an end thereof is coupled to the TaSiN layer 440.

The via plug 500 coupled to the resistive element 400 is in contact withthe TaSiN layer 440 at least at the end thereof. The via plug 500penetrates through the SiN layer 460, making contact with the TaSiNlayer 440. The end of the via plug 500 may penetrate into the TaSiNlayer 440. Where the resistive element 400 includes the TaN layer 420,the end of the via plug 500 may penetrate into the TaN layer 420. Thatis, the end of the via plug 500 is only required to be electricallycoupled to the TaSiN layer 440.

A barrier layer 540 is disposed over the sidewall and bottom of each viaplug 500. The barriers layer is, for example, a TiN/Ti layer. The TiNlayer thereof is disposed over the sidewall and bottom of each via plug500. If the barrier layer 540 is a TiN/Ti layer, the adhesion betweenthe barrier layer 540 and the TaSiN layer 440 can be increased.

A metal 520 is disposed inside the barrier layer 540 of each via plug500. The metal 520 is, for example, Cu, W, or the like.

As shown in FIG. 1B, two via plugs 500 are coupled to both ends of theresistive element 400. The region between the two via plugs serves as aresistance portion 404 to be discussed later. In this way, the resistiveelement 400 can be disposed in the multilayer wiring of thesemiconductor device 10.

In the multilayer wiring, an additional interlayer insulating layer (notshown), wiring (not shown), and via plugs (not shown) may be disposedover the interlayer insulating layer 360. An electrode pad (not shown)may be disposed as the uppermost layer of the multilayer wiring.

FIG. 2 is a plan view showing the configuration of the semiconductordevice according to the first embodiment. FIG. 2 is a plan view whenFIG. 1B is viewed from above and shows only the TaSiN layer 440, the viaplugs 500, and the interlayer insulating layer 360 of FIG. 1B. The TaSiNlayer 440 is disposed in the interlayer insulating layer 360 and shownby a solid line.

As shown in FIG. 2, the resistive element 400 includes the contactportions 402 for coupling at least both ends of the TaSiN layer 440 tothe via plugs 500 and the resistance portion 404 between the contactportions 402.

The contact portions 402 are, for example, rectangular in plan view. Theshape of the contact portions 402 is not limited to a rectangle and maybe a circle. The via plugs 500 are disposed in the contact portions 402in plan view.

For example, the resistance portion 404 is formed so as to be smaller inwidth than the contact portions 402 in plan view. Further, theresistance portion 404 is linear. As a result, the resistive element 400has a small area but a high resistivity.

The width and length of the resistance portion 404 are designed suchthat the resistance portion 404 has the desired resistance. As a result,in the semiconductor device 10, the standard potential can be obtainedwith respect to a given current owing to the resistive element 400.

Where the elongated resistance portion 404 is formed as shown in FIG. 2,tensile stress may be applied to the resistance portion 404 owing tothermal stress in the manufacturing process. However, the amorphousTaSiN layer 440 can relax the tensile stress. This prevents cracks fromoccurring in the resistance portion 404.

Referring to FIG. 3, a circuit diagram of the semiconductor device 10according to the first embodiment will be described. FIG. 3 is a circuitdiagram showing the configuration of the semiconductor device 10according to the first embodiment. For example, the resistive element400 constitutes part of a band gap reference (BGR) circuit as follows.For example, the BGR circuit determines the output voltage of a powersupply IC. Details will be described below.

As shown in FIG. 3, this BGR circuit includes a constant current sourceI, three resistors R₁, R₂, and R₃, and three transistors Q₁, Q₂, and Q₃.The transistor Q₁ and the like are FETs or bipolar transistors disposedover the semiconductor substrate 100. The resistive element R1 and thelike are resistive elements 400 at least a surface layer of which is theTaSiN layer 440. The constant current source I is formed, for example,by shorting the gate and source of the above-mentioned FET together.

The constant current source I, the resistive element R₁, and thetransistor Q₁ are coupled together in series. The base and collector ofthe transistor Q₁ are shorted together. The resistive element R₂, thetransistor Q₂, and the resistive element R₃ are coupled together inseries in this order so as to be in parallel with the resistive elementR₁ and the transistor Q₁. Coupled to the collector of the transistor Q₁is the gate of the transistor Q₂. Coupled to the resistive element R₂,the transistor Q₂, and the resistive element R₃ in parallel is thetransistor Q₃. Coupled to the collector of the transistor Q₂ is the gateof the transistor Q₃. The potential between the emitter and collector ofthe transistor Q₃ is a reference voltage VREF.

The VREF of FIG. 3 is given by Formula (1) below.

$\begin{matrix}{\left\lbrack {{Formula}\mspace{14mu} 1} \right\rbrack \mspace{625mu}} & \; \\{V_{REF} = {V_{{BE}\; 3} + {\frac{R_{2}}{R_{3}}\left( {\frac{KT}{q}\ln \frac{R_{2}}{R_{1}}} \right)}}} & (1)\end{matrix}$

In Formula 1, V_(BE3) represents the voltage between the base andemitter of the transistor Q₃; R₁ to R₃ represent respective resistances;K represents the Boltzmann constant; q represents the elementary charge;and T represents the temperature.

The temperature coefficient of VREF is given by Formula (2) below on thebasis of Formula (1).

$\begin{matrix}{\left\lbrack {{Formula}\mspace{14mu} 2} \right\rbrack \mspace{625mu}} & \; \\{\frac{\partial V_{REF}}{\partial T} = {\frac{\partial V_{{BE}\; 3}}{\partial T} + {\frac{K}{q}\left( {\frac{R_{2}}{R_{3}}\ln \frac{R_{2}}{R_{1}}} \right)}}} & (2)\end{matrix}$

In Formula (2); the first term on the right side represents thetemperature coefficient of the base-emitter voltage. In general, thetemperature coefficient of the base-emitter voltage in a Sisemiconductor shows a negative value. Accordingly, by adjusting theshape of the resistive element 400, the resistances of the resistors R₁to R₃ are set such that the second term cancels out the first term. As aresult, a temperature-compensated (no-temperature dependent) referencevoltage VREF can be obtained. Further, the use of the resistive elements400 according to the first embodiment as the resistors R₁ to R₃ canreduce variations in temperature characteristics of the resistance. As aresult, a stable reference voltage circuit can be formed. If asecond-order temperature characteristic compensation circuit, athird-order temperature characteristic compensation circuit, and ahigher order temperature characteristic compensation circuit eachincluding the resistive elements 400 according to the first embodimentare disposed in addition to this reference voltage circuit, variationsin temperature characteristics of the output voltage can be furtherreduced.

The semiconductor device 10 including the resistive element 400 asdescribed above can also be used as, for example, a sense resistancecircuit for detecting the remaining charge of a Li ion battery.

Referring to FIGS. 4A and 7B, a method for manufacturing thesemiconductor device 10 according to the first embodiment will bedescribed. FIGS. 4A to 7B are sectional views showing the method formanufacturing the semiconductor device according to the firstembodiment. The method for manufacturing the semiconductor device 10includes the following steps. First, the TaN layer 420 is formed overthe first insulating layer (interlayer insulating layer 340).Subsequently, a Si-containing gas is applied to the TaN layer 420. Thus,at least a surface layer of the TaN layer 420 is modified to the TaSiNlayer 440 (silane application step). Subsequently, the interlayerinsulating layer 360 is formed over the first insulating layer(interlayer insulating layer 340) and the resistive element 400.Subsequently, the multiple via plugs 500 are formed in the interlayerinsulating layer 360 in such a manner that ends thereof are coupled tothe TaSiN layer 440. Details will be described below.

First, as shown in FIG. 4A, FETs are formed over the semiconductorsubstrate 100.

Specifically, first, the element isolation regions 120 are formed in thesemiconductor substrate 100 by LOCOS. Subsequently, the gate insulatinglayer 220 and the gate electrodes 240 are formed over the semiconductorsubstrate 100 so as to have the respective desired shapes. Subsequently,using the gate insulating layer 220 and the gate electrodes 240 asmasks, impurities are ion-implanted into the semiconductor substrate 100to form the extension regions 160. Subsequently, the sidewall insulatinglayer 260 is formed over both sidewalls of the gate insulating layer 220and those of the gate electrodes 240. Subsequently, using the gateinsulating layer 220, the gate electrodes 240, and the sidewallinsulating layer 260 as masks, impurities are ion-implanted into thesemiconductor substrate 100 to form the diffusion regions 140. In thisway, the FETs are formed over the semiconductor substrate 100. Further,the liner insulating layer 320 is formed over the semiconductorsubstrate 100 having the FETs formed thereover.

Subsequently, as shown in FIG. 4B, the first insulating layer, theinterlayer insulating layer 340, is formed over the liner insulatinglayer 320 by CVD. If the interlayer insulating layer 340 is a low-kfilm, a SiCN layer or the like may be formed over the interlayerinsulating layer 340.

Subsequently, as shown in FIG. 5B, the TaN layer 420 is formed over theentire surface of the first insulating layer, the interlayer insulatinglayer 340, by reactive sputtering. At this time, a Ta target is used,and a nitrogen gas is used as a reactive gas.

As described above, the resistivity of the TaN layer 420 variesaccording to the composition ratio Ta/N. Accordingly, the resistivity ofthe TaN layer 420 is controlled by adjusting the flow rate of thenitrogen gas in this reactive sputtering to obtain the desiredcomposition ratio Ta/N. Thus, the resistivity of the TaN layer 420,which is the source of the TaSiN layer 440 to be discussed later, can becontrolled so that the TaSiN layer 440 will have the desiredresistivity. The TaN layer 420 is formed with a thickness of 50 nm.

Subsequently, a Si-containing gas is applied to the TaN layer 420 tomodify at least a surface layer of the TaN layer 420 to the TaSiN layer440 (silane application step). That is, the TaSiN layer 440 is amodified layer formed by applying a Si-containing gas to the TaN layer420.

“Applying a Si-containing gas” in the silane application step refers toapplying to the TaN layer 420 a Si-containing gas which is convertedinto plasma using radio frequency waves, light, or the like. ThisSi-containing plasma gas is highly reactive and, for example, reactswith the TaN layer 420 to modify it to silicide. In other words, theSi-containing gas is applied to the TaN layer 420 to dope the TaN layer420 with Si. As seen, applying the Si-containing plasma gas to thesurface layer of the TaN layer 420 allows at least the surface layer ofthe TaN layer 420 to be modified to the TaSiN layer 440.

The “Si-containing gas” is preferably a Si-containing gas including noorganic substituent group. On the other hand, organic Si-containinggases such as tetramethylsilane (Si(CH₃)₄) and tetraethoxysilane(Si(OC₂H₅)₄) are undesirable since carbon (C) may enter the TaSiN layer440. Specific examples of the Si-containing gas include monosilane(SiH₄) and disilane (Si₂H₆).

The silane application step is performed with the semiconductorsubstrate 100 heated to, e.g., 200° C. or more and 400° C. or less.

In this silane application step, the resistivity, the resistancetemperature coefficient, and thickness of the TaSiN layer 440 arecontrolled on the basis of the above-mentioned composition ratio andresistivity of the TaN layer 420 by adjusting the application amount ofthe Si-containing gas. Accordingly, the reactivity, resistancetemperature coefficient, and thickness of the TaSiN layer 440 can becontrolled by controlling the reactivity and resistance temperaturecoefficient of the TaN layer 420 in the reactive sputtering, as well ascan be controlled in the silane application step. That is, thecharacteristics of the TaSiN layer 440 can be controlled in two stages.

Another conceivable method for forming the TaSiN layer 440 is to form itby reactive co-sputtering while using Ta and Si targets and usingnitrogen as a reactive gas. However, performing co-sputtering asdescribed above involves adjusting various conditions such as electricpower to be applied to the two targets, the flow rate of the reactivegas, pressure during film formation, and the like. It is extremelydifficult to optimize the film formation conditions so that the TaSiNlayer 440 has the desired characteristics. In this embodiment, on theother hand, the TaSiN layer 440 is formed by applying the Si-containinggas to the previously formed TaN layer 420 having the desiredcomposition ratio in the silane application step. This makes it possibleto form the TaSiN layer 440 having the desired characteristics moreeasily than by performing co-sputtering as described above.

In the silane application step, a plasma CVD apparatus for forming aSiO₂ film or SiN film may be used. Accordingly, the same apparatus asthat used in the step of forming the SiN layer 460 to be discussed canbe used.

Specifically, in this silane application step, the SiN layer 460 isformed over the TaN layer 420, and the TaSiN layer 440 is formed overthe interface between the SiN layer 460 and the TaN layer 420. That is,when the SiN layer 460 is formed over the TaN layer 420, theSi-containing gas is necessarily applied to the surface layer of the TaNlayer 420. This allows the TaSiN layer 440 to be formed over theinterface between the SiN layer 460 and the TaN layer 420. Note that theSiN layer 460 is formed over the entire surface of the TaN layer 420.

For example, the SiN layer 460 is formed with a thickness of e.g., 20 nmover the TaN layer 420. Thus, the Si-containing gas is applied to theTaN layer 420 to a 10 nm depth. As a result, the TaSiN layer 440 isformed with a thickness of 5 nm.

As shown in FIG. 5B, the TaSiN layer 440 and the SiN layer 460 arepatterned in a step after the silane application step. First, aphotoresist film (not shown) is applied to the SiN layer 460.Subsequently, pattering is performed in such a manner that the resistiveelement 400 has the desired shape, by exposing the photoresist film tolight and developing it. Subsequently, the TaN layer 420, the TaSiNlayer 440, and the SiN layer 460 are etched by reactive ion etching(RIE). Subsequently, the photoresist film is peeled off. In this way,the resistive element 400 is patterned.

Subsequently, as shown in FIG. 6A, the interlayer insulating layer 360is formed over the first insulating layer, the interlayer insulatinglayer 340, and over the resistive element 400 by CVD.

Subsequently, as shown in FIG. 6B, multiple via holes 502 are formed byetching the interlayer insulating layer 340 and the interlayerinsulating layer 360 by RIE. At this time, some via holes 502 aredisposed so as to overlap the diffusion regions 140 of the FETs in planview. Further, two via holes 502 are disposed in the contact portions402 of the resistive element 400 in plan view.

At this time, the etching for forming the via holes 502 is stopped onthe respective top surfaces of the liner insulating layer 320 and theSiN layer 460. That is, the liner insulating layer 320 and the SiN layer460 serve as etching stopper films. As shown in FIG. 6B, even when theresistive element 400 is disposed at a different height from those ofthe FETs, formation of the via holes 502 can be stopped simultaneouslyby forming the top surface of the SiN layer 460 serving as an etchingstopper film at a higher position.

Subsequently, as shown in FIG. 7A, the liner insulating layer 320 andthe SiN layer 460 are etched by RIE so that the via holes 502 penetratetherethrough. At this time, the etching conditions are adjusted so thatends of the via holes 502 come into contact with the TaSiN layer 440.

Subsequently, as shown in FIG. 7B, the barrier layer 540 is formedinside the via holes 502 and over the interlayer insulating layer 360. ATiN layer and a Ti layer are formed in this order to form the barrierlayer 540.

Subsequently, the metal 520 is disposed over the barrier layer 540 ofthe via holes 502 by CVD so as to fill the via holes 502. The metal 520is, for example, W. The material for the metal 520 is, for example, WF₆.A metal such as Cu may be disposed by plating after forming a seed layer(not shown) over the barrier layer 540 in the via holes 502.

Subsequently, the surface of the interlayer insulating layer 360 isflattened by chemical mechanical polishing (CMP). In this way, the viaplugs 500 are formed.

In the multilayer wiring, an additional interlayer insulating layer (notshown), wiring (not shown), and via plugs (not shown) may be formed overthe interlayer insulating layer 360. Further, an electrode pad (notshown) may be formed as the uppermost layer of the multilayer wiring.

Although not shown, the semiconductor device 10 is packaged in thefollowing steps. First, the semiconductor substrate 100 obtained in theabove-mentioned process is diced to form semiconductor chips (notshown). Subsequently, the semiconductor chips are mounted over the diepad of a lead frame (not shown). Subsequently, electrode pads of thesemiconductor chips and the inner lead are coupled together usingbonding wires. Subsequently, the lead frame is sealed using a sealingresin. Subsequently, unwanted leads are cut off. Subsequently, outerleads are bent so as to have the desired shapes. In this way, thesemiconductor device 10 is obtained.

Next, effects of the first embodiment will be described.

According to the first embodiment, the resistive element 400 at leastthe surface layer of which is the TaSiN layer 440 is disposed over thefirst insulating layer, the interlayer insulating layer 340. The viaplugs 500 are formed in the interlayer insulating layer 360 disposedover the first insulating layer (interlayer insulating layer 340) andthe resistive element 400. Ends of two via plugs 500 are coupled to theTaSiN layer 440. Thus, the semiconductor device 10 that includes theresistive element 400 having a high resistivity and a small temperaturecoefficient of resistance in the interlayer insulating layer (interlayerinsulating layer 340, interlayer insulating layer 360, or the like) canbe provided.

Second Embodiment

FIGS. 8A and 8B are diagrams showing the configuration of the resistiveelement 400 according to a second embodiment. The second embodiment isthe same as the first embodiment except that the composition ratio ofthe TaSiN layer 440 changes in such a manner that the Si concentrationbecomes higher toward the surface layer of the TaSiN layer 440. Detailswill be described below.

FIG. 8A shows the resistive element 400 according to the secondembodiment. In the second embodiment, the composition ratio Si/(Ta+Si)of the TaSiN layer 440 changes. Since the resistive element 400 mayinclude no portion serving as the TaN layer 420, FIG. 8A does not showthe TaN layer 420.

In FIG. 8A, the length of the TaSiN layer 440 starting from the bottomsurface of the SiN layer 460 is represented by L (nm).

FIG. 8B shows the distribution of the composition ratio Si/(Ta+Si) ofthe TaSiN layer 440. The horizontal axis represents the length of theTaSiN layer 440 from the bottom surface of the SiN layer 460, L (nm).The vertical axis represents the composition ratio Si/(Ta+Si) of theTaSiN layer 440.

As shown in FIG. 8B, the composition ratio of the TaSiN layer 440changes in such a manner that the Si concentration becomes higher towardthe surface layer. In this embodiment, the TaSiN layer 440 is formed byforming the TaN layer 420 with a thickness of 100 nm and then performingthe silane application step.

For X of FIG. 8B, the composition ratio Si/(Ta+Si) decreasesmonotonously and linearly, starting from the bottom of the SiN layer460. If a composition ratio for obtaining the desired resistivity ortemperature coefficient of resistance is predetermined, the via plugs500 are formed to the length L where the composition ratio is obtained.

For Y of FIG. 8B, the composition ratio Si/(Ta+Si) decreasesmonotonously and parabolically, starting from the bottom surface of theSiN layer 460.

For Z of FIG. 8B, the composition ratio of Si/(Ta+Si) changes in a rangeof 0≦L≦50 nm. Accordingly, L>50 nm means the TaN layer 420. In this way,the TaSiN layer 440 is formed over the desired length L. The TaN layer420 may remain in the portion exceeding the length. The distributionwhere the composition ratio changes may be other than thesedistributions.

A method for manufacturing the semiconductor device 10 according to thesecond embodiment is the same as that according to the first embodimentexcept that the TaSiN layer 440 is formed in the silane application stepin such a manner that the composition ratio changes so that the Siconcentration becomes higher toward the surface layer.

In the subsequent step of forming the via plugs 500, the via plugs 500are formed until reaching the TaSiN layer 440 having the desiredcomposition ratio. As a result, the resistive element 400 having thedesired resistivity and temperature coefficient of resistance is formed.

If it is difficult to form the TaSiN layer 440 where the compositionratio changes as described above by performing the silane applicationstep once, the TaSiN layer 440 having the above-mentioned compositionratios may be formed by repeating the silane application step multipletimes after forming the TaN layer 420.

While, in the second embodiment, the composition ratio changes so thatthe Si concentration decreases monotonously, the composition ratio maychange in a step-wise manner.

According to the second embodiment, the composition ratio of the TaSiNlayer 440 changes so that the Si concentration becomes higher toward thesurface layer thereof. Thus, a resistive element 400 having anyresistivity and temperature coefficient of resistance can be provided.

Third Embodiment

FIGS. 9A and 9B are diagrams showing the configuration of the resistiveelement 400 according to a third embodiment. The third embodiment is thesame as the first embodiment except that the composition ratio is thesame across the TaSiN layer 440. Details will be described below.

FIG. 9A shows the resistive element 400 according to the thirdembodiment. In the third embodiment, the TaSiN layer 440 is formed bymodifying the entire TaN layer 420.

As with FIG. 8B, FIG. 9B shows the distribution of the composition ratioSi/(Ta+Si) of the TaSiN layer 440.

As shown in FIG. 9B, the composition ratio Si/(Ta+Si) of the TaSiN layer440 is kept constant at, e.g., 40%. This composition ratio can become acomposition ratio for obtaining the desired resistivity and temperaturecoefficient of resistance.

A method for manufacturing the semiconductor device 10 according to thethird embodiment is the same as that according to the first embodimentexcept that the TaSiN layer 440 is formed in such a manner that thecomposition ratio is the same across the TaSiN layer 440.

If it is difficult to form the TaSiN layer 440 having the samecomposition ratio across itself as described above by performing thesilane application step once, the TaSiN layer 440 having the samecomposition ratio may be formed by repeating the silane application stepmultiple times after forming the TaN layer 420.

According to the third embodiment, the composition ratio of the TaSiNlayer 440 is constant. Thus, a resistive element 400 that has a constantresistivity and temperature coefficient of resistance without dependingon the positions at which ends of the via plugs 500 are formed can beprovided.

Fourth Embodiment

FIGS. 10A and 10B are diagrams showing the configuration of thesemiconductor device 10 according to a fourth embodiment. The fourthembodiment is the same as the first embodiment except that the resistiveelement 400 is bent multiple times in plan view. Details will bedescribed below.

FIG. 10A is a plan view showing the configuration of the semiconductordevice 10 according to the fourth embodiment. FIG. 10A shows only theTaSiN layer 440, the via plugs 500, and the interlayer insulating layer360 of the semiconductor device 10.

As shown in FIG. 10A, the resistance portion 404 of the resistiveelement 400 is bent multiple times in plan view. In other words, theresistance portion 404 having a small width and a long length is formedso as to be meandering. The angle of the bend is not limited to anyparticular angle and is, for example, 90°.

FIG. 10B shows a sectional view taken along line C-C′ FIG. 10A. As shownin FIG. 10B, the contact portions 402 and the resistance portion 404 areformed in the same layer. Vias 500 are coupled to the contact portions402. The resistance portion 404 is formed with a width smaller than thecontact portions 402.

According to the fourth embodiment, the resistive element 400 is formedso as to be bent multiple times. Thus, the length of the resistanceportion 404 can be increased. As a result, the resistance of theresistive element 400 can be increased.

While the resistive element 400 is formed in the same layer in thefourth embodiment, it may be bent in a sectional direction acrossmultiple interlayer insulating layers (not shown).

Fifth Embodiment

FIG. 11 is a sectional view showing the configuration of thesemiconductor device 10 according to a fifth embodiment. The fifthembodiment is the same as the first embodiment except that the firstinsulating layer is the element isolation region 120. Details will bedescribed below.

As shown in FIG. 11, the first insulating layer may be the elementisolation region 120. The TaSiN layer 440 is formed over the elementisolation region 120. The TaSiN layer 440 is formed, for example, bymodifying the entire TaN layer 420.

The liner insulating layer 320 for covering the FETs can serve also as aSiN layer (not shown) for applying a Si-containing gas to the TaN layer420.

A method for manufacturing the semiconductor device 10 according to thefifth embodiment is the same as that according to the first embodimentexcept for the following points.

In FIG. 4A, the TaN layer 420 is formed before forming the linerinsulating layer 320. The TaN layer 420 may be formed before the stepsof forming the gate insulating layer 220, the gate electrodes 240, andthe sidewall insulating layer 260.

Subsequently, the liner insulating layer 320 is formed over the gateinsulating layer 220, the gate electrodes 240, and the sidewallinsulating layer 260, as well as over the TaN layer 420. This step canserve also as the “silane application step” in the first embodiment.

In this silane application step, the TaN layer 420 is modified to theTaSiN layer 440, starting from the surface layer and side surfacesthereof. If a uniform resistance distribution is desired, it ispreferred to modify the entire TaN layer 420 to the TaSiN layer 440.

Later steps are the same as those in the first embodiment.

According to the fifth embodiment, the first insulating layer is theelement isolation region 120. Thus, the liner insulating layer 320 forcovering the FETs can serve also as a SiN layer (not shown) for applyinga Si-containing gas to the TaN layer 420.

While the embodiments of the present invention have been described withreference to the drawings, the embodiments are illustrative only.Various configurations other than those described above can be employed.

1-10. (canceled)
 11. A method for manufacturing a semiconductor apparatus, comprising: forming a TaN layer over a first insulating layer; performing a silane application process of modifying at least a surface layer of the TaN layer to a TaSiN layer by applying a Si-containing gas; forming an interlayer insulating layer over the first insulating layer and the TaSiN layer; and forming a plurality of via plugs having ends coupled to the TaSiN layer in the interlayer insulating layer.
 12. The method for manufacturing a semiconductor apparatus according to claim 11, wherein the silane application process comprises forming the TaSiN layer in such a manner that a composition ratio of the TaSiN layer changes so that a Si concentration becomes higher toward a surface layer of the TaN layer.
 13. The method for manufacturing a semiconductor apparatus according to claim 11, wherein the silane application process comprises forming a SiN layer over the TaN layer and forming the TaSiN layer over an interface between the SiN layer and the TaN layer.
 14. The method for manufacturing a semiconductor device according to claim 13, the method comprising: in forming a TaN layer, forming the TaN layer over an entire surface of the first insulating layer; in the silane application process, forming the SiN layer over an entire surface of the TaN layer; and after the silane application process, patterning the TaSiN layer in the same process as the SiN layer. 